A three-dimensional integrated circuit (LSI) has been proposed with a view to integrating a semiconductor device (semiconductor integrated circuit device) on a much larger scale and speeding up the device more. In the three-dimensional LSI, substrates are electrically connected to one another using through electrodes called Through Silicon Vias (TSVs).
In the three-dimensional LSI, after an upper and a lower substrate are pressed against each other to pressure-bond bumps together, the space between substrates is filled with adhesive, thereby laminating the substrates together. However, this method might do heavy damage to elements in the LSI when pressure is applied to the upper and lower substrates. When the space between substrates is narrow, it is difficult to fill the space with adhesive.
To overcome the above problems, JP-A 2005-197339 (KOKAI) has disclosed the following method. First, a through hole is made in a substrate (wafer). An insulating film is formed on the inner surface of the through hole. After the underside of the substrate is polished, an insulating layer is formed on the underside of the substrate. Then, after the insulating layer on the underside is patterned, the substrates are laminated together. Thereafter, the through hole is filled with conductive material, thereby electrically connecting the substrates with each other. However, since the insulting layer formed on the underside of the substrate with large roughness is pattered, a problem arises: sufficient processing accuracy cannot be obtained.
As described above, it has been difficult to produce a three-dimensional LSI effectively.